– Experience with HDL (Verilog / VHDL) from 1,5 years;
– At least 1 year of expertise with C;
– University degree in technical sciences;
– Technical English (higher level is advantage).
– High salary, additional bonuses;
– Financial support for non-resident candidates;
– Official employment or private entrepreneurship;
– Medical insurance;
– Paid vacation and sick leave;
– Free lunches;
– Free English courses;
– Career and professional development;
– Gym / pool / health treatments;
– Convenient office location (Kyiv);
– Good working place with the most up-to-date equipment.
Please, send your CV marked «RTL Design Engineer» in the subject via e-mail: